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preliminary rev. 1.1e '99.02.10 HD66421 (ram-provided 160 channel 4-level grey scale driver for dot matrix graphics lcd) description the HD66421 drives and controls a dot matrix graphic lcd(liquid crystal display) using a bit-mapped method. it provides a highly flexible display through its on-chip display ram, in which each two bits of data can be used to turn on or off one dot on lcd panel with four-level grey scale. a single HD66421 can display a maximum of 160x100 dots using its powerful display control functions. it can display only eight lines out of one hundred lines. this function realize low power consumption because high voltage for driving lcd is not needed. an mpu can access HD66421 at any time, because the mpu operations are asynchronous with the HD66421's system clock and display operation. its low-voltage operation at 2.2 to 5.5v and standby function provides low power -dissipation, making the HD66421 suitable for small portable device applications. features ?built-in bit-mapped display ram: 30kbits (160 x 100 x 2 bits) ?grey scale display: pwm four-level grey scale can be selected from 32 levels ?grey scale memory management: packed pixel ?monochrome display: two planes can be selected. one plane is displayed while the other plane is being written. ?partial display: eight-lines data can be displayed in any place ?an 80-system mpu interface ?power supply voltage for operation : 2.2v to 5.5v ?power supply voltage for lcd : 18 v max. ?selectable multiplex duty ratio: 1/8, 1/64, 1/80, 1/100 ?lcd driving alternating cycle: 7, 11, 13 lines or flame ?built-in oscillator: external resister ?low power consumption: ?circuits for generating lcd driving voltage : contrast control, operational amplifier, and resistive dividers ?internal resistive divider: programmable bias rate ?32-level programmable contrast control ?wide range of instructions reversible display, display on/off, vertical display scroll, blink, reversible address, read-modify-write mode ?package: tcp type no. HD66421tb0 hcd66421bp package tcp die with gold bump ordering information HD66421 1
preliminary rev. 1.1e '99.02.10 HD66421 note: this figure is not drawn to a scale com100 com99 com98 com51 seg160 seg159 seg158 com50 seg3 seg2 seg1 com49 com3 com2 com1 pin arrangement i/o,power supply pins lcd drive signal output pins gnd1 vlcd1 vcc1 v5o v4o v3o v2o v1o gref irefm irefp vlcd2 vlcd3 vcc2 gnd2 gnd3 vcc3 osc1 osc2 osc co dcon cl1 flm m m/s res cs rs wr rd vcc4 gnd4 db0 db1 db2 db3 db4 db5 db6 db7 vcc5 gnd5 vcc6 vlcd4 gnd6 2
preliminary rev. 1.1e '99.02.10 HD66421 pad location coordinate no. pad name x y no. pad name x y no. pad name x y 1 com1 -4217 1731 31 com31 -4217 230 61 seg11 -4217 -1299 2 com2 -4217 1681 32 com32 -4217 179 62 seg12 -4217 -1349 3 com3 -4217 1631 33 com33 -4217 129 63 seg13 -4217 -1399 4 com4 -4217 1581 34 com34 -4217 79 64 seg14 -4217 -1449 5 com5 -4217 1531 35 com35 -4217 29 65 seg15 -4217 -1499 6 com6 -4217 1481 36 com36 -4217 -21 66 seg16 -4217 -1549 7 com7 -4217 1430 37 com37 -4217 -71 67 seg17 -4217 -1599 8 com8 -4217 1380 38 com38 -4217 -121 68 seg18 -4217 -1649 9 com9 -4217 1330 39 com39 -4217 -171 69 seg19 -4217 -1699 10 com10 -4217 1280 40 com40 -4217 -221 70 seg20 -4217 -1749 11 com11 -4217 1230 41 com41 -4217 -271 71 seg21 -4217 -1799 12 com12 -4217 1180 42 com42 -4217 -321 72 seg22 -4217 -1849 13 com13 -4217 1130 43 com43 -4217 -371 73 seg23 -4217 -1899 14 com14 -4217 1080 44 com44 -4217 -421 74 seg24 -4217 -1949 15 com15 -4217 1030 45 com45 -4217 -471 75 dummy a -4217 -2082 16 com16 -4217 980 46 com46 -4217 -521 76 dummy 1 -4029 -2082 17 com17 -4217 930 47 com47 -4217 -571 77 dummy 2 -3907 -2082 18 com18 -4217 880 48 com48 -4217 -621 78 dummy 3 -3827 -2082 19 com19 -4217 830 49 com49 -4217 -671 79 dummy 4 -3619 -2082 20 com20 -4217 780 50 com50 -4217 -721 80 dummy 5 -3497 -2075 21 com21 -4217 730 51 seg1 -4217 -798 81 dummy 6 -3419 -2075 22 com22 -4217 680 52 seg2 -4217 -848 82 seg25 -2822 -2082 23 com23 -4217 630 53 seg3 -4217 -898 83 seg26 -2772 -2082 24 com24 -4217 580 54 seg4 -4217 -948 84 seg27 -2722 -2082 25 com25 -4217 530 55 seg5 -4217 -998 85 seg28 -2672 -2082 26 com26 -4217 480 56 seg6 -4217 -1049 86 seg29 -2622 -2082 27 com27 -4217 430 57 seg7 -4217 -1099 87 seg30 -2572 -2082 28 com28 -4217 380 58 seg8 -4217 -1149 88 seg31 -2522 -2082 29 com29 -4217 330 59 seg9 -4217 -1199 89 seg32 -2472 -2082 30 com30 -4217 280 60 seg10 -4217 -1249 90 seg33 -2422 -2082 gnd7 com1 seg24 dummya dummy1 gnd8 dummy12 dummy8 seg137 com100 gnd1 gnd2 type code HD66421 pad arrangement chip size : 8.99 x 4.72 mm coordinate : pad center origin : chip center bump size : gnd1, gnd8, dummy a, dummy b 70 x 70 ? power, i/o (pad no. 276 to 321) 50 x 70 ? com1 - 100, seg1 - 160, dummy1 -12 35 x 50 ? 3
preliminary rev. 1.1e '99.02.10 HD66421 no. pad name x y no. pad name x y no. pad name x y 91 seg34 -2372 -2082 141 seg84 220 -2082 191 seg134 2722 -2082 92 seg35 -2322 -2082 142 seg85 270 -2082 192 seg135 2772 -2082 93 seg36 -2272 -2082 143 seg86 320 -2082 193 seg136 2822 -2082 94 seg37 -2222 -2082 144 seg87 370 -2082 194 dummy 7 3419 -2075 95 seg38 -2172 -2082 145 seg88 420 -2082 195 dummy 8 3497 -2075 96 seg39 -2121 -2082 146 seg89 470 -2082 196 dummy 9 3619 -2082 97 seg40 -2071 -2082 147 seg90 520 -2082 197 dummy 10 3827 -2082 98 seg41 -2021 -2082 148 seg91 570 -2082 198 dummy 11 3907 -2082 99 seg42 -1971 -2082 149 seg92 620 -2082 199 dummy 12 4029 -2082 100 seg43 -1921 -2082 150 seg93 670 -2082 200 dummy b 4217 -2082 101 seg44 -1871 -2082 151 seg94 720 -2082 201 seg137 4217 -1949 102 seg45 -1821 -2082 152 seg95 770 -2082 202 seg138 4217 -1899 103 seg46 -1771 -2082 153 seg96 820 -2082 203 seg139 4217 -1849 104 seg47 -1721 -2082 154 seg97 870 -2082 204 seg140 4217 -1799 105 seg48 -1671 -2082 155 seg98 921 -2082 205 seg141 4217 -1749 106 seg49 -1621 -2082 156 seg99 971 -2082 206 seg142 4217 -1699 107 seg50 -1571 -2082 157 seg100 1021 -2082 207 seg143 4217 -1649 108 seg51 -1521 -2082 158 seg101 1071 -2082 208 seg144 4217 -1599 109 seg52 -1471 -2082 159 seg102 1121 -2082 209 seg145 4217 -1549 110 seg53 -1421 -2082 160 seg103 1171 -2082 210 seg146 4217 -1499 111 seg54 -1371 -2082 161 seg104 1221 -2082 211 seg147 4217 -1449 112 seg55 -1321 -2082 162 seg105 1271 -2082 212 seg148 4217 -1399 113 seg56 -1271 -2082 163 seg106 1321 -2082 213 seg149 4217 -1349 114 seg57 -1221 -2082 164 seg107 1371 -2082 214 seg150 4217 -1299 115 seg58 -1171 -2082 165 seg108 1421 -2082 215 seg151 4217 -1249 116 seg59 -1121 -2082 166 seg109 1471 -2082 216 seg152 4217 -1199 117 seg60 -1071 -2082 167 seg110 1521 -2082 217 seg153 4217 -1149 118 seg61 -1021 -2082 168 seg111 1571 -2082 218 seg154 4217 -1099 119 seg62 -971 -2082 169 seg112 1621 -2082 219 seg155 4217 -1049 120 seg63 -921 -2082 170 seg113 1671 -2082 220 seg156 4217 -998 121 seg64 -870 -2082 171 seg114 1721 -2082 221 seg157 4217 -948 122 seg65 -820 -2082 172 seg115 1771 -2082 222 seg158 4217 -898 123 seg66 -770 -2082 173 seg116 1821 -2082 223 seg159 4217 -848 124 seg67 -720 -2082 174 seg117 1871 -2082 224 seg160 4217 -798 125 seg68 -670 -2082 175 seg118 1921 -2082 225 com51 4217 -721 126 seg69 -620 -2082 176 seg119 1971 -2082 226 com52 4217 -671 127 seg70 -570 -2082 177 seg120 2021 -2082 227 com53 4217 -621 128 seg71 -520 -2082 178 seg121 2071 -2082 228 com54 4217 -571 129 seg72 -470 -2082 179 seg122 2121 -2082 229 com55 4217 -521 130 seg73 -420 -2082 180 seg123 2172 -2082 230 com56 4217 -471 131 seg74 -370 -2082 181 seg124 2222 -2082 231 com57 4217 -421 132 seg75 -320 -2082 182 seg125 2272 -2082 232 com58 4217 -371 133 seg76 -270 -2082 183 seg126 2322 -2082 233 com59 4217 -321 134 seg77 -220 -2082 184 seg127 2372 -2082 234 com60 4217 -271 135 seg78 -170 -2082 185 seg128 2422 -2082 235 com61 4217 -221 136 seg79 -120 -2082 186 seg129 2472 -2082 236 com62 4217 -171 137 seg80 -70 -2082 187 seg130 2522 -2082 237 com63 4217 -121 138 seg81 70 -2082 188 seg131 2572 -2082 238 com64 4217 -71 139 seg82 120 -2082 189 seg132 2622 -2082 239 com65 4217 -21 140 seg83 170 -2082 190 seg133 2672 -2082 240 com66 4217 29 4
preliminary rev. 1.1e '99.02.10 HD66421 no. pad name x y no. pad name x y no. pad name x y 241 com67 4217 79 284 gref 2722 2195 309 db0 -1948 2195 242 com68 4217 129 2642 2195 -2028 2195 243 com69 4217 179 285 irefm 2541 2195 310 db1 -2131 2195 244 com70 4217 230 2461 2195 -2211 2195 245 com71 4217 280 286 irefp 2360 2195 311 db2 -2310 2195 246 com72 4217 330 2280 2195 -2390 2195 247 com73 4217 380 287 vlcd2 2179 2195 312 db3 -2494 2195 248 com74 4217 430 2099 2195 -2574 2195 249 com75 4217 480 288 vlcd3 2009 2195 313 db4 -2672 2195 250 com76 4217 530 1929 2195 -2752 2195 251 com77 4217 580 289 vcc2 1830 2195 314 db5 -2856 2195 252 com78 4217 630 1750 2195 -2936 2195 253 com79 4217 680 290 gnd3 1647 2195 315 db6 -3034 2195 254 com80 4217 730 1567 2195 -3114 2195 255 com81 4217 780 291 gnd4 1494 2195 316 db7 -3218 2195 256 com82 4217 830 1414 2195 -3298 2195 257 com83 4217 880 292 vcc3 1316 2195 317 vcc5 -3398 2195 258 com84 4217 930 1236 2195 -3478 2195 259 com85 4217 980 293 osc1 947 2195 318 gnd6 -3581 2195 260 com86 4217 1030 867 2195 -3661 2195 261 com87 4217 1080 294 osc2 766 2195 319 vcc6 -3739 2195 262 com88 4217 1130 686 2195 -3819 2195 263 com89 4217 1180 295 osc 585 2195 320 vlcd4 -3910 2195 264 com90 4217 1230 505 2195 -3990 2195 265 com91 4217 1280 296 co 404 2195 321 gnd7 -4091 2195 266 com92 4217 1330 324 2195 -4217 2195 267 com93 4217 1380 297 dcon 223 2195 268 com94 4217 1430 143 2195 269 com95 4217 1481 298 cl1 41 2195 270 com96 4217 1531 -39 2195 271 com97 4217 1581 299 flm -140 2195 272 com98 4217 1631 -220 2195 273 com99 4217 1681 300 m -321 2195 274 com100 4217 1731 -401 2195 275 gnd1 4217 2195 301 m/s -502 2195 4091 2195 -582 2195 277 vlcd1 3992 2195 302 res -683 2195 3912 2195 -763 2195 278 vcc1 3809 2195 303 cs -864 2195 3729 2195 -944 2195 279 v5o 3628 2195 304 rs -1045 2195 3548 2195 -1125 2195 280 v4o 3447 2195 305 wr -1226 2195 3367 2195 -1306 2195 281 v3o 3266 2195 306 rd -1407 2195 3186 2195 -1487 2195 282 v2o 3084 2195 307 vcc4 -1587 2195 3004 2195 -1667 2195 283 v1o 2903 2195 308 gnd5 -1770 2195 2823 2195 -1850 2195 gnd2 276 gnd8 322 5
preliminary rev. 1.1e '99.02.10 HD66421 pin description number pin name of pins i/o connected to description vcc1-6, gnd1-6 12 - power supply vcc: +2.2v to +5.5v, gnd: 0v vlcd1-4 4 - power supply power supply to lcd driving circuit v1o, v2o, 5 - v1 to v5 of several levels of power to the lcd driving outputs. v3o,v4o, HD66421 master HD66421 outputs these levels to the slave v5o HD66421. osc 1 i, oscillator must be connected to external resister when using osc1,osc2 2 i/o resister or r-c oscillation. when using an external clock, it must external clock be input to the osc terminal. co 1 o osc of slave clock output HD66421 dcon 1 o external dc/dc controls on/off switch of external dc/dc convertor convertor cl1 1 i/o cl1 of HD66421 line clock flm 1 i/o flm of HD66421 frame signal m 1 i/o m of HD66421 converts lcd driving outputs to ac m/s 1 i vcc or gnd specifies master/slave mode. res 1 i - reset the lsi internally when drive low. cs 1 i mpu select the lsi, specifically internal registers (index and data registers) when driven low. rs 1 i mpu select one of the internal registers; select the index register when driven low and data registers when driven low. wr 1 i mpu inputs write strobe; allows a write access when driven low. rd 1 i mpu inputs read strobe; allows a read access when driven low. db7 to db0 8 i/o mpu 8-bits three-state bidirectional data bus; transfer data between the hd66420 and mpu through this bus. seg1 to 160 o lcd output column drive signals seg160 com1 to 100 o lcd output row drive signals com100 irefp 1 - vcc irefm 1 - gref 1 - gnd 6 power supply for internal operation amplifier bias current for internal operational amplifier power supply for internal operation amplifier external resistor
preliminary rev. 1.1e '99.02.10 HD66421 register list cs rs index reg. bits register name r/w data bits 4 3 2 1 0 7 6 5 4 3 2 1 0 1 - - - - - - - 0 0 - - - - - ir index register w ir4 ir3 ir2 ir1 ir0 0 1 0 0 0 0 0 r0 control register 1 w rmw disp stby pwr amp rev holt adc 0 1 0 0 0 0 1 r1 control register 2 w bis1 bis0 wls gray dty1 dty0 inc blk 0 1 0 0 0 1 0 r2 x address register w xa5 xa4 xa3 xa2 xa1 xa0 0 1 0 0 0 1 1 r3 y address register w ya6 ya5 ya4 ya3 ya2 ya1 ya0 0 1 0 0 1 0 0 r4 display ram access register r/w d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 0 1 0 1 r5 display start line register w st6 st5 st4 st3 st2 st1 st0 0 1 0 0 1 1 0 r6 blink start line register w bsl6 bsl5 bsl4 bsl3 bsl2 bsl1 bsl0 0 1 0 0 1 1 1 r7 blink end line register w bel6 bel5 bel4 bel3 bel2 bel1 bel0 0 1 0 1 0 0 0 r8 blink register 1 w bk0 bk1 bk2 bk3 bk4 bk5 bk6 bk7 0 1 0 1 0 0 1 r9 blink register 2 w bk8 bk9 bk10 bk11 bk12 bk13 bk14 bk15 0 1 0 1 0 1 0 r10 blink register 3 w bk16 bk17 bk18 bk19 0 1 0 1 0 1 1 r11 partial display block register w pb3 pb2 pb1 pb0 0 1 0 1 1 0 0 r12 gray scale palette 1 (0,0) w gp14 gp13 gp12 gp11 gp10 0 1 0 1 1 0 1 r13 gray scale palette 2 (0,1) w gp24 gp23 gp22 gp21 gp20 0 1 0 1 1 1 0 r14 gray scale palette 3 (1,0) w gp34 gp33 gp32 gp31 gp30 0 1 0 1 1 1 1 r15 gray scale palette 4 (1,1) w gp44 gp43 gp42 gp41 gp40 0 1 1 0 0 0 0 r16 contrast control register w cc4 cc3 cc2 cc1 cc0 0 1 1 0 0 0 1 r17 plane selection register w 0 1 1 0 0 1 0 r18 reserved - 0 1 1 0 0 1 1 r19 reserved - 0 1 1 0 1 0 0 r20 reserved - 0 1 1 0 1 0 1 r21 reserved - 0 1 1 0 1 1 0 r22 reserved - 0 1 1 0 1 1 1 r23 reserved - 0 1 1 1 0 0 0 r24 reserved - 0 1 1 1 0 0 1 r25 reserved - 0 1 1 1 0 1 0 r26 reserved - 0 1 1 1 0 1 1 r27 reserved - 0 1 1 1 1 0 0 r28 reserved - 0 1 1 1 1 0 1 r29 reserved - 0 1 1 1 1 1 0 r30 reserved - 0 1 1 1 1 1 1 r31 reserved - 7 cm1 cm0 cle mon dsel psel
preliminary rev. 1.1e '99.02.10 HD66421 rmw rmw = 1: read-modify-write mode; address is incremented only after write access rmw = 0: address is incremented after both write and read access disp disp = 1: display on disp = 0: display off stby stby = 1:internal operation and power circuit halt; display off stby = 0: normal operation pwr pwr = 1: output 'high' from dcon pwr = 0: output 'low' from dcon amp amp = 1: op amp enable amp = 0: op amp disable rev rev = 1: reverse display rev = 0: normal display holt holt = 1: internal operation stops, oscillator works holt = 0: internal operation starts adc adc = 1: data in x address h'0 is output from seg160 adc = 0: data in x address h'0 is output from seg1 bis1, 0 bis1, 0 = (1,1): 1/8 lcd drive levels bias ratio bis1, 0 = (1,0): 1/9 lcd drive levels bias ratio bis1, 0 = (0,1): 1/10 lcd drive levels bias ratio bis1, 0 = (0,0): 1/11 lcd drive levels bias ratio wls wls = 1: 6-bit data is valid wls = 0: 8-bit data is valid gray gray = 1: grayscale palette is available(gray scales can be selected from 32-levels) gray = 0: grayscale palette is not available(4-gray scales fixed) dty1, 0 dty1, 0 = (1,1): 1/8 display duty cycle - partial display dty1, 0 = (1,0): 1/64 display duty cycle dty1, 0 = (0,1): 1/80 display duty cycle dty1, 0 = (0,0): 1/100 display duty cycle inc inc = 1: x address is incremented for each access inc = 0: y address is incremented for each access 8
preliminary rev. 1.1e '99.02.10 HD66421 mon dsel dsel = 1: plane 1 is displayed dsel = 0: plane 0 is displayed psel psel = 1: plane 1 is read/written from the mpu psel = 0: plane 0 is read/written from the mpu mon = 1: monochrome display mon = 0: four levels gray scale display 9 cm1, 0 cm1, 0 = (1,1): alternative cycle is 13 lines. cm1, 0 = (1,0): alternative cycle is 11lines. cm1, 0 = (0,1): alternative cycle is 7 lines. cm1, 0 = (0,0): alternative cycle is 1 frame. blk blk = 1: blink function is used blk = 0: blink function is not used cle cle = 1: co,cl1,flm,m stop in master mode. they are high-z. cle = 0: co,cl1,flm,m are operating in master mode. normal operation.
preliminary rev. 1.1e '99.02.10 HD66421 column driver y decoder x decoder row counter 320 x 80bit display memory level shifter data latch2 data latch1 com1 com50 seg1 seg160 com51 com100 x address counter start line register attribute comparator blink end line register blink start line register control register mpu interface display line counter rd wr cs rs db7 -db0 block diagram row driver oscillator osc res osc2 lcd driver power supply, contrast control v3o v2o v5o v4o vlcd y address counter data buffer timing generator grey scale selector grey scale palette 320 160 level shifter grey scale pattern generator contrast control register flm m cl1 co dcon v1o osc1 m/s 5 decoder 320 320 row driver level shifter i/o control blink registers mpx 10
preliminary rev. 1.1e '99.02.10 HD66421 system description the HD66421 can display a maximum of 160 x 100 dots (ten 16x16-dot characters x 6 lines) four-level gray scale or four colour lcd panel. four levels of gray scale can be selected from 32-levels, so the appropriate 4-level gray scale can be displayed. and monochrome display can be selected from two planes. one plane is displayed while the other plane is being written. the HD66421 can reduce power dissipation without affecting display because data is retained in the display ram even during standby modes. an lcd system can be configured simply by attaching external power supply, capacitors and resistors (figure 1) since the HD66421 incorporates power circuits. com1 to com50 HD66421 lcd panel mpu 8 seg1 to seg160 cs rs rd wr db7 to db0 com51 to com100 dc/dc convertor figure 1 system block diagram 11
preliminary rev. 1.1e '99.02.10 HD66421 mpu interface the HD66421 can interface directly to an mpu through an 8-bit data bus or through an i/o port (figure 2). the mpu can access the HD66421 internal registers independently of internal clock timing. the index register can be directly accessed but the other registers (data registers) cannot. before accessing a data register, its register number must be written to the index register. once written, the register number is held until it is rewritten, enabling the same register to be consecutively accessed without having to rewrite to the register number for each access. an example of a register access sequence is shown in figure 3. figure 3 8-bit data transfer sequence rd wr db7 to db0 write index register rs cs write data register write index register read data register read data register data data data data data data write data register c0 c1 c2 c3 a0 - a7 cs rs rd wr db0 - db7 h8/325 HD66421 8 a) interface through bus a15 - a0 a0 rd wr d0 - d7 cs rs rd wr db0 - db7 z80 HD66421 8 figure 2 8-bit mpu interface examples b) interface through i/o port decoder 12
preliminary rev. 1.1e '99.02.10 HD66421 dot-matrix display 50-channel row output 160-channel column output 50-channel row output row outputs from both sides of lcd 160 x 100 HD66421 lcd driver configuration row and column outputs: the HD66421's row outputs is only both sides. in any case, each output's function is fixed; com1 to com100 output row signals and seg1 to seg160 output column signals. figure 4 common outputs from both sides 13 com51 to com100 com1 to com50 seg1 to seg160
preliminary rev. 1.1e '99.02.10 HD66421 column address inversion according to lcd driver layout: the HD66421 can always display data in address h'0 on the top left of an lcd panel regardless of where it is positioned with respect to the panel. this is because the HD66421 can invert the positional relationship between display ram addresses and lcd driver output pins by inverting ram addresses. specifically, the HD66421 outputs data in address h'0 from seg1 when the adc bit in control register 1 is 0, and from seg160 otherwise. here. the scan direction of row output is also inverted according to the situation. as shown in figure 6. note that addresses and scan direction are inverted when data is written to the display ram, and thus changing the adc bit after data has been written has no effect. therefore. hardware control bits such as adc must be set immediately after reset is canceled, and must not be set while data is being displayed. figure 5 lcd driver layout and ram addresses : 1/100 duty cycle com1 com50 lcd panel com100 com51 b) adc = 1 seg1 seg2 seg3 seg158 seg159 seg160 seg157 seg156 seg155 seg154 seg153 com100 com51 com1 com50 a) adc = 0 h'0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg158 seg159 seg160 lcd panel dty1 common segment dty0 adc 0 1 com1 ? com50, com100 ? com51 com51 ? com100, com50 ? com1 h'00 ? seg1 h'00 ? seg160 0 1 com1 ? com40, com100 ? com61 com61 ? com100, com40 ? com1 h'00 ? seg1 h'00 ? seg160 0 1 h'00 ? seg1 h'00 ? seg160 0 1 8 com depend on r11 8 com depend on r11 h'00 ? seg1 h'00 ? seg160 0 0 0 1 1 0 1 1 table 1 scanning direction and ram address h'1 h'0 h'1 HD66421 HD66421 com1 ? com32, com100 ? com69 com69? com100, com32 ? com1 14
preliminary rev. 1.1e '99.02.10 HD66421 dot-matrix display 50-channel row output 160-channel column output 50-channel row output 320 x 100 HD66421 (master) multi-lsi operation using multiple HD66421s provides the means for extending the number of display dots. note the following items when using the multi-lsi operation. (1) the master lsi and the slave lsi must be determined; the m/s pin of the master lsi must be set high and the m/s pin of the slave lsi must be set low. 2) the master lsi supplies the flm, m, cl1 and clock signals to the slave lsi via the corresponding pins, which synchronizes the slave lsi with the master lsi. (3) all control bits of slave lsi must be set with the same data with that of the master lsi. figure 6 configuration using two HD66421s 160-channel column output HD66421 (slave) cl1 flm m cl1 flm m osc co osc osc1 co osc1 open (4) all lsis must be set to lcd off in order to turn off the display. (5) the standby function of slave lsi must be started up first, and that of the master lsi must be terminated first. (6) the power supply circuit of slave lsi stop working, so v1 to v5 levels are supplied from the master lsi. if the internal power supply circuit can not drive two lsis, use an external power supply circuit. figure 6 shows the configuration using two HD66421s and table 2 lists the differences between master and slave modes. table 2 comparison between master and slave modes item master mode slave mode pin m/s osc co flm, m, cl1 registers must be set high oscillation is active output output signals must be set low oscillation is active high-z input signals v1o to v5o v1o to v5o r0, r2 to r15,r17 r1:bis1, 0 r1:other r16 valid valid invalid valid valid valid invalid valid 15 power supply circuit invalid valid m/s m/s vcc
preliminary rev. 1.1e '99.02.10 HD66421 display ram configuration and display the HD66421 incorporates a bit-mapped display ram. it has 320 bits in the x direction and 100 bits in the y direction. the 320 bits are divided into forty 8-bit groups. as shown in figure 7, data written by the mpu is stored horizontally with the msb at the far left and the lsb at the far right. the consecutive two bits control one pixel of lcd in 4-level gray scale mode, this means that one 8-bits data contains data which controls four pixels. one bit of memory designates one dot of display in the monochrome display mode. the adc bit of control register 1 can control the positional relationship between x addresses of the ram and lcd driver output (figure 8). specifically. the data in address h'0 is output from seg1 when the adc bit in control register 1 is 0, and from seg160 otherwise. here. data in each 8-bit group is also inverted. because of this function, the data in x address h'0 can be always displayed on the top left of an lcd panel with the msb at the far left regardless of the lsi is positioned with respect to the panel. in this case, db7, db5, db3 and db1 are more significant bit in consecutive two bits. h'00 h'01 h'0 h'1 h'27 x addresses seg1 seg160 lcd drive signal output (a) mon = 0, adc = 0, wls= 0 (b) mon = 0, adc = 1, wls= 0 figure 7 display ram data and display in gray scale mode figure 8 display ram configuration in gray scale mode h'62 h'63 h'00 h'01 h'0 h'26 h'27 seg1 seg160 h'62 h'63 y address msb msb lcd drive signal output y address x addresses seg1 seg2 seg3 seg4 1 1 1 0 0 1 0 0 0 0 0 1 1 0 1 1 y0 y1 d b 7 d b 1 lcd panel display ram seg157 seg158 deg159 seg160 1 1 1 0 0 1 0 0 0 0 0 1 1 0 1 1 y0 y1 d b 7 d b 0 lcd panel display ram d b 6 d b 4 d b 5 d b 2 d b 3 d b 1 d b 6 d b 5 d b 4 d b 3 d b 2 d b 0 (a) mon = 0, adc = 0, wls= 0 (b) mon = 0, adc = 1 , wls= 0 seg160 seg1 16
preliminary rev. 1.1e '99.02.10 HD66421 h'00 h'01 h'0 h'2 h'26 x address seg1 seg160 (a) mon = 1, adc = 0 (b) mon = 1, adc = 1 h'62 h'63 h'00 h'01 h'0 h'24 h'26 seg1 seg160 h'62 h'63 y address msb msb seg1 seg2 seg3 seg4 1 1 1 0 0 1 0 0 0 0 0 1 1 0 1 1 y0 y1 d b 7 d b 1 lcd panel display ram 1 1 1 0 0 1 0 0 0 0 0 1 1 0 1 1 y0 y1 d b 6 d b 0 lcd panel display ram d b 7 d b 4 d b 5 d b 2 d b 3 d b 1 d b 6 d b 5 d b 4 d b 3 d b 2 d b 0 (a) mon = 1, adc = 0, wls= 0 (b) mon = 1, adc = 1, wls= 0 seg160 x address y address seg5 seg6 seg7 seg8 seg160 seg159 seg158 seg157 seg156 seg155 seg154 seg153 seg1 17 figure 9 display ram data and display in monochrome mode figure 10 display ram configuration in monochrome mode lcd drive signal output lcd drive signal output
preliminary rev. 1.1e '99.02.10 HD66421 word length the HD66421 can handle either 8- or 6-bits as a word. in the display memory, one x address is assigned to each word of 8- or 6-bits long in x direction. h'00 h'01 h'0 h'1 h'27 x addresses seg1 seg160 lcd drive signal output (a) address assignment when one word is 8 bits long (mon=0) h'62 h'63 h'00 h'01 h'35 h'1 h'0 seg1 seg160 h'62 h'63 y address msb msb lcd drive signal output y address x addresses h'34 (b) address assignment when one word is 6 bits long (mon=0) 8 bits 6 bits figure 11 display ram addresses in gray scale mode (a) wls= 1, adc = 0, mon= 0 h'35's bit7,6, and 3 to 0 are disable . (b) wls= 1, adc = 1 mon= 0 h'0's bit7 to 2 are disable. 1 1 1 0 0 1 0 0 0 1 1 0 y0 y1 d b 5 display ram 1 0 0 0 1 1 d b 5 d b 4 d b 0 d b 4 d b 3 d b 2 d b 1 d b 0 h'35 h'0 1 1 1 0 0 1 0 0 0 1 1 0 y0 y1 d b 1 display ram 1 0 0 0 1 1 d b 1 d b 0 d b 4 d b 0 d b 3 d b 2 d b 5 d b 4 h'0 h'35 18 when the 6-bits mode is selected, only data on db5 to db0 are used and data on db7 and db6 are discarded. this word length is only applied to data to internal ram. the word length of internal register is always 8-bits figure 12 display ram bits map at 6-bits mode (c) wls= 1, adc = 0, mon= 1 h'34's bit7,6, and 1,0 are disable . (d) wls= 1, adc = 1, mon= 1 h'0's bit7 to 4 are disable. 1 1 1 0 0 1 0 0 0 1 1 0 y0 y1 d b 5 display ram 1 0 0 0 1 1 d b 5 d b 4 d b 0 d b 4 d b 3 d b 2 d b 1 d b 0 h'34 h'0 1 1 1 0 0 1 0 0 0 1 1 0 y0 y1 d b 0 display ram 1 0 0 0 1 1 d b 0 d b 1 d b 5 d b 1 d b 2 d b 3 d b 4 d b 5 h'0 h'34 0 0 1 1 0 0 1 1 d b 3 d b 2 d b 2 d b 3
preliminary rev. 1.1e '99.02.10 HD66421 plane 1 plane 0 dsel psel figure 13 memory planes in monochrome display mode h'00 h'01 h'0 h'2 h'26 seg1 seg160 h'62 h'63 y address 19 lcd drive signal output figure 14 memory addresses in monochrome display mode monochrome display mode the HD66421 can control monochrome display. this mode is set when mon is set to 1. two plane of display can be selected in this mode using two bits data for gray scale. one plane can be selected with psel bit for access from the cpu and with dsel bit for display. theses two operations are independent to each other, thus oneplane can be rewritten while the other plane is displayed. this means no flicker during being rewritten. the address area is mapped to even address from h'0 to h'26 in monochrome mode and this address area is the same for both planes. the plane 0 is accessed when psel is cleared to 0 and the plane 1 is selected when psel is set to 1. the plane 0 is displayed when dsel is cleared to 0 and the plane 1 is displayed when dsel is set to 1.
preliminary rev. 1.1e '99.02.10 HD66421 0 0 0 1 1 0 1 1 7 6 5 4 3 2 1 0 bit frc control circuit grey scale/colour palette physical memory lcd display state configuration of display data bit packed pixel method for grey scale display and super reflective colour display, multiple bits are needed for one pixel. in the HD66421, two bits are assigned to one pixel, enabling a four-level grey scale display and four colour display. one address, eight bits, specifies four pixels, and pixel bits 0 and 1 for gray scale are managed as consecutive bits in one byte. 0 0 0 0 1 0 1 0 7 6 5 4 3 2 1 0 4 pixels/address address: n address: n + 1 when grey scale display data is manipulated in bit units, one memory access is sufficient, which enables smooth high-speed data rewriting. the bit data to input to pin db7, db5, db3 and db1 become msb and the bit data to input via pin db6, db4, db2 and db0 are lsb. gray scale/colour palette the HD66421 uses pwm, pulse width modulation, technique for gray scale display. a period of one line is divided into thirty-one or four and HD66421 outputs turn-on levels for one period and turn-off levels for rest of these period. this technique changes gray scale on monochrome display and colour on super reflective colour panel. the characteristics of these panel vary with different panel. to allow for this, the HD66421 designed to generate 32-levels gray scale levels and provides palette registers that assign desired levels to certain of the four colours, gray = 0, or generate dedicated 4-level grayscale , gray = 1. using the palette registers to select any 4 out of 32 levels of applied voltages enables an optimal grayscale/colour display. because of this grayscale technique using 32-levels gray scale needs higher clock rate. if 32-levels gray scale is not needed, lower clock rate can be used. table 3 shows default value of palette registers and table 4 and 5 show relationship between value of a palette register and grayscale level. db7, 5, 3, 1 db6, 4, 2, 0 register name default value 0 0 0 1 1 0 1 1 grayscale palette 1 grayscale palette 2 grayscale palette 3 grayscale palette 4 0 0 0 0 0 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 table 3 default value of palette registers figure 15 packed pixel method 20
preliminary rev. 1.1e '99.02.10 HD66421 value 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 table 4 value of a palette register and grayscale levels (gray= 0) 0 1/31 2/31 3/31 grayscale level 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4/31 5/31 6/31 7/31 8/31 9/31 10/31 11/31 12/31 13/31 14/31 15/31 16/31 17/31 18/31 19/31 20/31 21/31 22/31 23/31 24/31 25/31 26/31 27/31 28/31 29/31 30/31 1 default r12 default r13 default r14 default r15 db7,5,3,1 0 0 0 1 1 0 1 1 table 5 grayscale levels (gray= 1) 0 1/3 2/3 1 grayscale level db6,4,2,0 21
preliminary rev. 1.1e '99.02.10 HD66421 access to internal registers and display ram access to internal registers by the mpu: the internal registers includes the index register and data registers. the index register can be accessed by driving both the cs and rs signals low. to access a data register, first write its register number id to the index register with rs set to 0, and then access the data register with rs set to 1 . once written, the register number is held until it is rewritten, enabling the same register to be consecutively accessed without having to rewrite to the register number for each access. some data registers contain unused bits; they should be set to 0. note that all data registers except the display memory access register can only be written to. access to display ram by the mpu: to access the display ram, first write the ram address desired to the x address register (r2) and the y address register (r3). then read/write the display memory access register (r4). memory access by the mpu is independent of memory read by the HD66421 and is also asynchronous with the HD66421's clock, thus enabling an interface independent of HD66421's internal operations. however, when reading. data is temporarily latched into a h66421's buffer and then output next time, a read is performed in a subsequent cycle. this means that a dummy read is necessary after setting x and y addresses. the memory read sequence is shown in figure 16. x and y addresses are automatically incremented after each memory access according to the inc bit value in control register 2; therefore, it is not necessary to update the addresses for each access. figure 16 shows two cases of incrementing display ram address. when the inc bit is 0, the y address will be incremented up to h'7f with the x address unchanged. however, actual memory is valid only within h'00 to h'4f; accessing an invalid address is ignored. when the inc bit is 1 , the x address will be incremented up to h'27 or h'35 according to wls bit with the y address unchanged. after address h'27 or h'35, the x address will be returned to h'00; accessing more than forty bytes causes rewriting to the same address. [n] [m] data[n,m] data[n,m+1] undetermined h'02 h'03 h'04 wr input data output data dummy read [n,*] [n,m] [n,m+1] [n,m+2] [*,*] address rs rd figure 16 display ram read sequence x address y address 22
preliminary rev. 1.1e '99.02.10 HD66421 display ram reading by lcd controller: data is read by the HD66421 to be displayed asynchronously with accesses by the mpu. however, because simultaneous access could damaging data in the display ram, the HD66421 internally arbitrates access timing; access by the mpu usually has priority and so access by the HD66421 is placed between accesses by the mpu. accordingly, an appropriate time must be secured (see the given electrical characteristics between two accesses by the mpu). (a) inc = 0 h'0 h'1 h'27 h'00 h'01 h'7f h'28 h'35 wls= 0 wls= 1 (b) inc = 1, mon= 0 h'0 h'1 h'27 h'00 h'01 h'02 h'63 h'28 h'35 wls= 0 wls= 1 figure 17 display address increment wls= 0 wls= 1 h'63 valid area invalid area valid area (wls= 1) invalid area 23 (c) inc = 1, mon= 1 h'0 h'2 h'26 h'00 h'01 h'02 h'63 h'28 h'34 wls= 0 wls= 1 wls= 0 wls= 1
preliminary rev. 1.1e '99.02.10 HD66421 read-modify-write: x- or y-address is incremented after reading form or writing data to the display ram at normal mode. however, x- or y-address is not incremented after reading data from the display ram at read-modify-write mode. the data which is read from the display ram may be modified and written to the same start end set x-address set y-address dummy read read data write data finish modifying no yes address incremented figure 18 the flow chart for read-modify-write address without re-setting the address. data is temporarily latched into a HD66421's buffer and then output next time a read is performed in a subsequent cycle. this means that the dummy read is necessary after every cycle. this sequence is shown in figure 18. 24
preliminary rev. 1.1e '99.02.10 HD66421 arbitration control the HD66421 controls the arbitration between draw access and display access. the draw access read and write display data of display memory incorporated in the HD66421. the display access outputs display data to the liquid crystal panel. the draw access has the priority over display access, so continuous access is enabled without having the system to wait. for arbitration control, draw access is recognized as valid when cs and wr/rd are low. when draw and display access occur at the same time, draw access is executed prior to display access. display access is executed between two draw access during display access period. if a period of one draw access is longer than that of display access, display access will not be executed properly. if this condition happens frequently, flicker will be seen on the display. the low level width of wr and rd must be less than the period of display access - 450ns. 25 draw access draw access display access period cs wr rd figure 19 definition of draw access display access period cs wr display access (min. 450ns) figure 21 wr low level width draw access period of 4 clocks (22us approx. ) * memory access period of 4 clocks (22 s approx ) * display access period cs wr memory access display access draw access figure 20 memory access when display and draw access occur at the same time * in the case of fosc = 180khz * in the case of fosc = 180khz period of 4 clocks - 450ns
preliminary rev. 1.1e '99.02.10 HD66421 vertical scroll function the HD66421 can vertically scroll a display by varying the top raster to be displayed. which is specified by the display start raster register. figure 22 and 23 show vertical scroll examples. as shown, when the top raster to be displayed is set to l, data in y address h'0 is displayed on the 100th raster. to display another frame on the 100th raster, therefore, data in y address h'0 must be modified after setting the top raster. when display duty is less than 100, for example 1/80, data of address h'50 is displayed after address h'4f. figure 22 vertical scroll : 1/100duty cycle h'00 h'01 h'02 h'03 h'04 h'05 h'06 h'07 h'08 h'09 h'0a h'60 h'61 h'62 h'63 y-address top raster to be displayed = 0 top raster to be displayed = 2 y-address h'00 h'01 h'62 h'63 h'0b h'0c h'02 h'03 h'04 h'05 h'06 h'07 h'08 h'09 h'0a y-address top raster to be displayed = 1 h'0b h'01 h'02 h'03 h'04 h'05 h'06 h'07 h'08 h'09 h'0a h'00 h'61 h'62 h'63 26
preliminary rev. 1.1e '99.02.10 HD66421 y-address y-address figure 23 vertical scroll : 1/80duty cycle top raster to be displayed = 0 top raster to be displayed = 1 top raster to be displayed = 2 y-address h'00 h'01 h'02 h'03 h'04 h'05 h'06 h'07 h'08 h'09 h'0a h'4c h'4d h'4e h'4f h'0b h'01 h'02 h'03 h'04 h'05 h'06 h'07 h'08 h'09 h'0a h'50 h'4d h'4e h'4f h'0b h'0c h'02 h'03 h'04 h'05 h'06 h'07 h'08 h'09 h'0a h'50 h'4e h'4f h'51 27
preliminary rev. 1.1e '99.02.10 HD66421 partial display function the HD66421 can display only a part of a full display. the duty ratio of this partial display is 1/8 and rest of display is scanned with unselected levels. the position of this partial display can be located at any position with using partial display position register. to launch this mode, following processes are needed: (1) supplied voltage to vlcd must be cut off, pwr bit can be used if external voltage supplier is controlled with dcon output (r0) (2) set dty bits (r1) (3) set display position (r11) (4) set contrast level (r16) the clock frequency may be 220khz at normal display mode. when a partial display is driven, oscillation frequency will be 18khz, 1/12.5 of that of normal display mode. this function is useful for lower power dissipation. to change clock frequency, follow the process which is showed in figure 28. warning: vlcd must be cut off when partial display mode is launched. vcc is supplied to lcd driving circuit instead of vlcd. so if vlcd is supplied externally during partial display mode, vcc short-circuit to vlcd. 28 figure 24 partial display table 6 partial display block h'00 h'01 h'02 h'03 h'04 h'05 h'06 h'07 h'08 h'09 h'0a h'0b r11 com1 com9 com17 com25 com33 com41 com100 com92 com84 com76 com68 com60 ? ? ? ? ? ? ? ? ? ? ? ? com8 com16 com24 com32 com40 com48 com93 com85 com77 com69 com61 com53 com1 com9 com17 com25 com33 com41 com100 com92 com84 com76 com68 com60 ? ? ? ? ? ? ? ? ? ? ? ? com8 com16 com24 com32 com40 com48 com93 com85 com77 com69 com61 com53 adc= 0 adc= 1 start line r5 r5+7 y address display ram h'00 h'63 r11=h'04 lcd panel abcd abcd com33 com40 com1 com100 com49,com50 (not used) com51,com52 (not used)
preliminary rev. 1.1e '99.02.10 HD66421 blink function the HD66421 can blink a specified area on the dot-matrix display. blinking is achieved by repeatedly turning on and off the specified area at a frequency of one sixty-fourth the frame frequency. for example, when the frame frequency is 80 hz. the area is turned on and off every 0.8 seconds. the area to be blinked can be designated by specifying vertical and horizontal positions of the area. the vertical position. or the rasters to be blinked, are specified by the blink start raster register (r6) and blink end raster register (r7). the horizontal position, or the dots to be blinked in the specified rasters, are specified by the blink registers r8, r9 and r10 in an 8-dot group; each data bit in the blink registers controls its corresponding 8-dots group. the relationship between the registers and blink area is shown in figure 25. setting the blk bit to 1 in control register 2 after setting the above registers starts blinking the designated area. note that since the area to be blinked is designated absolutely with respect to the display ram, it will move along with a scrolling display (figure 26). 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 blink start line (r6) blink end line (r7) blink registers r8 r9 display start raster = 0 blink start raster = 0 blink end raster = h'f figure 26 scrolling blink area blink area seg1 lcd seg9 seg17 seg25 seg33 seg41 seg49 seg57 seg65 seg73 seg81 seg89 seg97 seg105 seg113 seg121 seg129 seg137 seg145 seg153 0 0 0 1 seg160 d b 3 d b 2 d b 1 d b 0 r10 display start raster = h'5 blink start raster = h'5 blink end raster = h'f figure 25 blink area designation by blink control registers 29
preliminary rev. 1.1e '99.02.10 HD66421 com1-com100 seg1-seg160 display starts initiation cancellation figure 27 procedure for initiation and canceling a standby mode wait for oscillation and external power supply to stabilize set disp bit to 1 (control register 1) stby 1 1 output vlcd (display off) output vlcd (display off) signal name status table 7 output pin status during power down modes 0 output common signals (vlcd - gnd) 0 output segment signals (vlcd - gnd) power down modes the HD66421 has a standby function providing low power-dissipation, which is initiated by internal register settings. during standby mode, all the HD66421 functions are inactive and data in the display ram and internal registers except the disp bit are retained. however, only control registers can be accessed during standby mode. HD66421 has an another power down mode: partial display. in this mode only a part of display is active. however, this duty ratio is 1/8 so the external power supply for lcd drive will be inactive. the oscillator does not halt, thus dissipating more power than standby mode. table 6 lists the lcd driver output pin status during standby mode. figure 27 shows the procedure for initiating and canceling a standby mode and figure 28 shows the procedure for changing oscillator. note that these procedure must be strictly followed to protect data in the display ram. set holt bit to 1 (control register 1) set dty or gray bit to 1 (control register 2) internal operation stops oscillator 2 starts working figure 28 procedure for changing oscillator wait for oscillation to stabilize clear holt bit to 0 (control register 1) internal operation starts 30 set stby bit to 1 and amp bit to 0 (control register 1) clear stby and pwr bits to 0 and amp bit to 1 (control register 1) oscillator starts op amp power on internal operation starts standby mode oscillation halts op amp power off external power supply off
preliminary rev. 1.1e '99.02.10 HD66421 power on/off procedure figure 29 shows the procedure for turning the power supply on and off. this procedure must be boosting starts power on figure 29 procedure for turning power supply on/off turn on power (power-on reset) set pwr,amp bit to 1 (control register 1) write data to registers and ram as required set disp bit to 1 (control register 1) set cnf, adc, dty1, dty0, inc bits according to the operating mode (control register1 and 2) turn off power clear disp bit to 0 (control register 1) power off boosting halts strictly followed to prevent incorrect display because the HD66421 incorporates a power supply circuit. clear pwr,amp bit to 0 (control register 1) 31
preliminary rev. 1.1e '99.02.10 HD66421 oscillator the HD66421 incorporates two sets of r-c oscillator for two display modes: osc-osc1 oscillator is used for 32-levels gray scale display mode and osc-osc2 oscillator for 4-levels gray scale display mode. if the internal oscillator is not used, an appropriate clock signal must be externally input through the osc pin. in this case, the osc1 and osc2 pins must be left unconnected. oscillation resister must be placed near lsi, because if capacitance exists between osc and osc1 oscillator may not work properly. figure 30 shows oscillator connections. changing oscillator two oscillators are alternated automatically depending on modes. an external clock must be input from osc terminal at any modes. clock and frame frequency the HD66421 generates the frame frequency by dividing the input clock. clock frequency is determined with following equation: fosc = n * (duty ratio) * (frame frequency) n: 31 for 32-level gray scale display mode 3 for 4-level gray scale display mode the frame frequency is usually 70 to 90 hz; when the frame frequency is 70 hz, for example, the input clock frequency will be 220 khz for 32-level gray scale display mode, and 18khz for 4-level gray scale. lcd driving alternating cycle ac voltage needs to be applied to liquid crystals to prevent deterioration due to dc voltage. this alternated cycle is determied by setting alernating cycle register (r16); 7, 11, 13lines or flame. osc osc2 clock (open) osc osc1 HD66421 HD66421 a) external clock b) dual oscillator figure 30 oscillator connections rf1 osc1 (open) osc2 osc osc1 HD66421 c)single oscillator rf osc2 (open) rf2 32 0 0 0 0 0 0 0 0 frame 7 lines alternative cycle table 8 lcd alternative drive cycle 11 lines 13 lines cm1 cm0
preliminary rev. 1.1e '99.02.10 HD66421 power supply circuits HD66421 has following circuits for power supply circuit: operational amplifiers, resistive dividers, bias control circuit and contrast control circuit. lcd driving voltage, vlcd, must be generated externally. lcd drive voltage power supply levels: to drive the lcd, a 6-level power supply are necessary. these levels are generated internally or supplied from outside. when an internal voltage levels generator is chosen, external capacitors are needed to stabilize these levels. as the HD66421 incorporates operational amplifiers to these levels, this circuit gives better quality of display with less power consumption. this divided ratio is programmable. bias current of internal operational amplifier is determined with a resister which is inserted between irefm and gnd. this resister value is between 1m w and 5m w . larger resister value make less power consumption at internal operational amplifier. however, too large value loose operational margin of amplifiers. keep following relationship among voltage levels; contrast control: internal contrast control circuit can change the output voltage level of vlcd by setting data to contrast control register, r16. vlcd adjustable range are showed below; ?1/8 bias 0.73 * (vlcd-gnd) vlcd 0.988 * (vlcd-gnd) ?1/9 bias 0.82 * (vlcd-gnd) vlcd 0.993 * (vlcd-gnd) (example 1.) ?1/11 bias 0.79 * (vlcd-gnd) vlcd 0.992 * (vlcd-gnd) ? partial display 0.82 * (vcc-gnd) vcc 0.997 * (vcc-gnd) (example 2.) partail display function uses 1/4 bias ratio from vcc to gnd. 8 levels of contrast can be selected with data bit 2 to 0 of r16. 33 vcc 3 irefmp > irefm 3 gnd vlcd > vcc > gref 3 gnd vlcd 3 v1o 3 v2o 3 v3o 3 v4o 3 v5o 3 gref 3 gnd vlcd-vcc 3 1.0v irefp-irefm 3 1.0v vcc-gref 3 1.0v example.1 lcd bias level example 2. lcd bias level 1/80 duty display(1/9 bias, vlcd=12v,gnd=0v) partial display(1/4 bias,vcc=5v,gnd=0v) 0 1 2 3 4 5 6 7 8 9 10 11 12 contrast (r16) voltage [v] v1o v2o v3o v4o v5o 0 1f 7 f 17 0 1 2 3 4 5 contrast (r16) voltage [v] v1o v2o v3o v4o v5o 0 7 4 (maximum) (maximum) vlcd vcc
preliminary rev. 1.1e '99.02.10 HD66421 figure 31 power supply circuit - + - + - + - + v2o v3o v4o v5o iv1 iv2 iv3 iv4 gref r1 r1 r3 r1 r1 vlcd r2 contrast control circuit bias control v1o HD66421 dcon external voltage booster on/off vout - + iv5 r4 irefp irefm gnd vcc vlcd operational amplifier off resistive divider for partial display mode r r r r r1 = r r2 = 0.094r to 3r r3 = 4r to 7r r4 = 1m w to 5m w c1 = 1? to 3? resister for bias current of operational amplifier c1 c1 c1 c1 c1 34 lcd drive levels bias ratio: lcd driving levels bias ratio can be selected from 1/8, 1/9, 1/10 or 1/11. power supply: the HD66421 needs the external power supply for lcd driving circuit. if this power circuit has on/off control, the HD66421 controls the external power supply circuit by setting pwr bit. external power supply circuit: when the internal operational amplifier cannot fully drive the lcd panel used, v1o to v5o voltages can be supplied from external power supply circuit. here, the amp bit must be set to 1 to turn off the internal power supply circuit.
preliminary rev. 1.1e '99.02.10 HD66421 reset the low res signal initializes the HD66421, clearing all the bits in the internal registers. during reset. the internal registers cannot be accessed. note that if the reset conditions specified in the electric characteristics section are not satisfied, the HD66421 will not be correctly initialized. in this case, the internal registers of the HD66421 must be initialized by software. initial setting of internal registers: all the internal register bits are cleared to 0. details are listed below. - normal operation - oscillator is active; osc-osc1 is used - display is off - y address of display ram is incremented - 1/100 duty cycle - x and y addresses are 0 - data in address h'0 is output from the segl pin - blink function is inactive - operational amplifier is disabled initial setting of pins: bus interface pins during reset, the bus interface pins do not accept signals to access internal registers; data is undefined when read. lcd driver output pins during reset. all the lcd driver output pins (seg1 to segl61, com1 to com100) output vcc-level voltage, regardless of data value in the display ram, turning off the lcd. here, the output voltage is not alternated. note that the same voltage (vlcd) is applied to both column and row output pins to prevent liquid crystals from degrading. 35
preliminary rev. 1.1e '99.02.10 HD66421 internal registers the HD66421 has one index register and 18 data registers, all of which can be accessed asynchronously with the internal clock. all the registers except the display memory access register are write-only. accessing unused bits or addresses affects nothing; unused bits should be set to 0 when written to. index register (ir): the index register (figure 32) selects one of 18 data registers. the index register itself is selected when both the cs and rs signals are low. data bits 7 to 5 are unused; they should be set to 0 when written to. control register 1 (r0): control register 1 (figure 33) controls general operations of the HD66421. each bit has its own function as described below. rmw bit rmw = l: read-modify-write mode address is incremented only after write access rmw = 0: address is incremented after both write and read accesses disp bit disp = 1: display on disp = 0: display off (all lcd driver output pins output vlcd level) stby bit stby = l: internal operation and oscillation halt; display off stby = 0: normal operation pwr bit pwr = l: output high level from dcon terminal pwr = 0: output low level from dcon terminal this bit controls the external power supply for lcd driving outputs. amp bit amp = 1: op amp enable amp = 0: op amp disable rev bit rev = 1: reverse display rev = 0: normal display holt bit holt = l : internal operation stops holt = 0: internal operation starts adc bit adc = l: data in x address h'0 is output from seg160; row signals depend on duty. adc = 0: data in x address h'0 is output from seg1; row signals are scanned from com1. figure 32 index register (ir) data bit set value 7 6 5 4 3 2 1 0 figure 33 control register 1 (r0) rmw disp stby pwr amp rev holt adc data bit set value 7 6 5 4 3 2 1 0 register number 36
preliminary rev. 1.1e '99.02.10 HD66421 control register 2 (r1): control register 2 (figure 34) controls general operations of the HD66421. each bit has its own function as described below. bis1, bis0 bits bis1, 0 = (1, 1): 1/8 lcd drive levels bias ratio bis1, 0 = (1, 0): 1/9 lcd drive levels bias ratio bis1, 0 = (0, 1): 1/10 lcd drive levels bias ratio bis1, 0 = (0, 0): 1/11 lcd drive levels bias ratio wls bit wls = l: a word length is 6-bits wls = 0: a word length is 8-bits gray bit gray = l : 4-levels of gray scale are fixed gray = 0: 4-levels of gray scale are selected from 32-levels dty1,dty0 bits dty1, 0 = (1, 1): 1/8 display duty cycle; partial display mode dty1, 0 = (1, 0): 1/64 display duty cycle dty1, 0 = (0, 1): 1/80 display duty cycle dty1, 0 = (0, 0): 1/100 display duty cycle inc bit i nc = l: x address is incremented for each access inc = 0: y address is incremented for each access blk bit blk = 1: blink function is used blk = 0: blink function is not used the blink counter is reset when the blk bit is set to 0. it starts counting and at the same time initiates blinking when the blk bit is set to l. x address register (r2): the x address register (figure 35) designates the x address of the display ram to be accessed by the mpu. the set value must range from h'00 to h'27 in the case of 8-bit a word or range from h'00 to h'35 in the case of 6-bit a word; setting a greater value is ignored. the set address is automatically incremented each time the display ram is accessed; it is not necessary to update the address each time. data bits 7 and 6 are unused; they should be set to 0 when written to. when you use monochrome display, the set value must range the even number from h'00 to h'26 in the case of 8-bit a word or range from h'00 to h'34 in the case of 6-bit a word. y address register (r3): the y address register (figure 36) designates the y address of the display ram to be accessed by the mpu. the set value must range from h'00 to h'40; setting a greater value is ignored. the set address is automatically incremented each time the display ram is accessed; it is not necessary to update the address each time. data bit 7 is unused; it should be set to 0 when written to. data bit set value 7 6 5 4 3 2 1 0 figure 34 control register 2 (r1) wls gray dty1 dty0 inc blk data bit set value 7 6 5 4 3 2 1 0 figure 35 x address register (r2) xa5 data bit set value 7 6 5 4 3 2 1 0 figure 36 y address register (r3) ya6 xa4 xa3 xa2 xa1 xa0 ya5 ya4 ya3 ya2 ya1 ya0 bis0 bis1 37
preliminary rev. 1.1e '99.02.10 HD66421 display memory access register (r4): the display memory access register (figure 37) is used to access the display ram. if this register is write-accessed, data is directly written to the display ram. if this register is read-accessed, data is first latched to this register from the display ram and sent out to the data bus on the next read; therefore, a dummy read access is necessary after setting the display ram address. display start raster register (r5): the display start raster register (figure 38) designates the raster to be displayed at the top of the lcd panel. varying the set value scrolls the display vertically. the set value must be one less than the actual top raster and less than the duty ratio. if the value is set outside these ranges, data may not be displayed correctly. data bits 7 is unused; they should be set to 0 when written to. data bit set value 7 6 5 4 3 2 1 0 figure 37 display memory access register (r4) d7 d6 d5 d4 d3 d2 d1 d0 data bit set value 7 6 5 4 3 2 1 0 figure 38 display start raster register (r5) st5 st4 st3 st2 st1 st0 st6 blink start raster register (r6): the blink start raster register (figure 39) designates the top raster in the area to be blinked. the set value must be one less than the actual top raster and less than the duty ratio. if the value is set outside these ranges, operations may not be correct. data bits 7 is unused; they should be set to 0 when written to. blink end raster register (r7): the blink end register (figure 40) designates the bottom raster in the area to be blinked. the area to be blinked is designated by the blink registers, blink start raster register, and blink end raster register. the set value must be one less than the actual bottom raster and less than the duty ratio. it must also be greater than the value set in the blink start raster register. if an inappropriate value is set, operations may not be correct. data bits 7 is unused; they should be set to 0 when written to. data bit set value 7 6 5 4 3 2 1 0 figure 39 blink start raster register (r6) bsl5 bsl4 bsl3 bsl2 bsl1 bsl0 bsl6 data bit set value 7 6 5 4 3 2 1 0 figure 40 blink end raster register (r7) bel5 bel4 bel3 bel2 bel1 bel0 bel6 38
preliminary rev. 1.1e '99.02.10 HD66421 bit 4 is clock-enable bit. this bit sets to 1, the signal co,cl1,flm and m stop in master mode. they are high-z. data bits 7 and 5 are unused; they should be set to 0 when written to. gray scale palette registers (r12 to r15): the gray scale palette registers (figure 43) designate the grayscale level or colour. use these registers to enable an optimal grayscale or colour display. if gray bit is 1, these registers are inactive. data bits 7 to 5 are unused; they should be set to 0 when written to. data bit set value 7 6 5 4 3 2 1 0 figure 42 partial display start raster register (r11) pb3 pb2 pb1 pb0 blink registers (r8 to r10): the blink bit registers (figure 41) designate the 8-bit groups to be blinked. setting a bit to 1 blinks the correspond- ing 8-bit group. any number of groups can be blinked; setting all the bits to 1 will blink the entire lcd panel. these bits are valid only when the blk bit of control register 2 is 1. r10's data bits 7 to 4 are unused; they should be set to 0 when written to. partial display block register (r11): the partial display block register (figure 42) designates the block of partial display. it use from bit 3 to bit 0. data bit set value 7 6 5 4 3 2 1 0 figure 41 blink registers (r8, r9, r10) bk0 bk1 bk2 bk3 bk4 bk5 bk6 bk7 set value bk8 bk9 bk10 bk11 bk12 bk13 bk14 bk15 set value bk16 bk17 bk18 bk19 data bit set value 7 6 5 4 3 2 1 0 figure 43 grayscale palette registers (r12 to r15) gp14 gp13 gp12 gp11 gp10 set value gp24 gp23 gp22 gp21 gp20 set value gp34 gp33 gp32 gp31 gp30 set value gp44 gp43 gp42 gp41 gp40 r12 r13 r14 r15 39 r8 r9 r10 set value h'00 h'01 h'02 h'03 h'04 h'05 row no. com1 to com8 com9 to com16 com17 to com24 com25 to com32 com33 to com40 com41 to com48 set value h'06 h'07 h'08 h'09 h'0a h'0b row no. com100 to com93 com92 to com85 com84 to com77 com76 to com69 com68 to com61 com60 to com53 (adc= "0". if "1" , reverse direction) cle
preliminary rev. 1.1e '99.02.10 HD66421 gp14 gp13 gp12 gp11 gp10 gp24 gp23 gp22 gp21 gp20 gp34 gp33 gp32 gp31 gp30 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0 1/31 gray scale level table 9 grayscale levels 2/31 3/31 4/31 5/31 6/31 7/31 8/31 9/31 10/31 11/31 12/31 13/31 14/31 15/31 gp44 gp43 gp42 gp41 gp40 figure 44 contrast control register (r16) data bit set value 7 6 5 4 3 2 1 0 cc3 cc2 cc1 cc0 cc4 40 cm0 cm1 gp14 gp13 gp12 gp11 gp10 gp24 gp23 gp22 gp21 gp20 gp34 gp33 gp32 gp31 gp30 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 gray scale level 16/31 17/31 18/31 19/31 1 0 1 0 0 20/31 1 0 1 0 1 21/31 1 0 1 1 0 22/31 1 0 1 1 1 23/31 1 1 0 0 0 24/31 1 1 0 0 1 25/31 1 1 0 1 0 26/31 1 1 0 1 1 27/31 1 1 1 0 0 28/31 1 1 1 0 1 29/31 1 1 1 1 0 30/31 1 1 1 1 1 1 gp44 gp43 gp42 gp41 gp40 0 0 0 0 0 0 0 0 frame 7 lines alternative cycle table 10 lcd alternative drive cycle 11 lines 13 lines cm1 cm0 contrast control and lcd alternative drive cycle register (r16): the contrast control register (figure 44) designates the contrast level of lcd display. these bits change the voltage which is supplied to lcd drivers. the lcd alternative drive cycle register designates the number of lines that lcd drive outputs are alternated. data bits 7 is unused; they should be set to 0 when written to.
preliminary rev. 1.1e '99.02.10 HD66421 41 grayscale no. figure 45 lcd effective value 2.0 2.1 2.2 2.3 2.4 0 4 8 12 16 20 24 28 lcd effective value [v] lsi (no load) vlcd=15v, ta=25?c, 1/9 bias figure 45 shows characteristics of the lcd effective value against grayscale. this value is almost linear at all grayscale range without lcd panel. this linearity will be lost if lcd panel is connected. in this case, the four appropriate levels must be selected from grayscale no.1 to 31. lsi + lcdpanel r14(default) r13(default) 31
preliminary rev. 1.1e '99.02.10 HD66421 figure 46 plane selection register (r17) data bit set value 7 6 5 4 3 2 1 0 mon dsel psel plane selection register (r17): the plane selection register (figure 46) controls general operations of the HD66421. each bit has its own function as described below. mon bit mon = l: monochrome display mon = 0: 4-level gray scale display dsel bit desl = 1: plane 1 is displayed desl = 0: plane 0 is displayed psel bit pesl = 1: access to plane 1 from cpu pesl = 0: access to plane 0 from cpu 42 note when you use the monochrome display, you have to initialize the x-address to even number before access to display ram. and you alway have to use even number.
preliminary rev. 1.1e '99.02.10 HD66421 absolute maximum ratings item symbol ratings unit notes power supply logic circuit vcc -0.3 to +7.0 v 1 voltage lcd drive circuit vlcd -0.3 to +20.0 v input voltage 1 vt1 -0.3 to vcc+0.3 v 1, 2 input voltage 2 vt2 -0.3 to vlcd+0.3 v 1, 3 operating temperature topr -40 to +85 ? storage temperature tstg -55 to +110 ? 43 notes: 1 .measured relative to gnd 2 applies to pins m/s, osc, osc1, osc2, db7 to db0, rd, wr, cs, rs, res, cl1, m, flm 3 applies to pins v1o, v2o, v3o, v4o and v5o 4 if the lsi is used beyond its absolute maximum rating, it may be permanently damaged. it should always be used within the limits of its electrical characteristics to prevent malfunction or unreliability.
preliminary rev. 1.1e '99.02.10 HD66421 electrical characteristics dc characteristics (vcc=2.2 to 5.5v, gnd=0v, vlcd=6 to 18v, ta=-40 to +85? note 9) applicable measurement item symbol pins min. typ max unit condition notes i/o leakage iiol -1 - 1 ? vin=vcc to gnd 1 current v-pins leakage ivl -10 - 10 vin=gnd to vlcd 2 current driver on ron seg1 to seg160 com1 to com100 20 k w ion = 100? 3 resistance vlcd = 6v input high vih1 0.8xvcc - vcc v 1 voltage input low vil1 0 - 0.2xvcc v 1 voltage output high voh db7 to db0 0.8xvcc - vcc v ioh=-50? voltage output low vol db7 to db0 0 - 0.2xvcc v iol=50? voltage current idisp - t.b.d 5, 6 consumption during display current istb - 5, 7 consumption during standby 1 5 ? ? ? notes: 1 applies to pins: m/s, cs, rs, wr, rd, res, osc, db7 to db0, cl1, m and flm 2 applies to pins: v0o, v1o, v2o, v3o, v4o and v5o 3 indicates the resistance between one pin from seg1 to seg160,com1 to com100 from v1o to v5o v1o and v2o should be near vlcd level, and v3o to v5o should be near gnd level. all voltage must be within d v. d v is the range within which ron is stable. v1 to v4 levels should keep following condition:vlcd 3 v1o 3 v2o 3 v3o 3 v4o 3 v5o 3 gnd 5 input and output current are excluded. when a cmos input is floating, excess current flows from power supply to the input circuit. to avoid this, vih and vil must be held to vcc and gnd levels, respectively. the current which flows at resistive divider and lcd are excluded. vcc current ilcd - 5, 8 consumption in lcd drive part ? vcc vlcd 4 4 vcc = 3.0v rf = 180k w 4 applies to pins: db7-db0, co, cl1, m and flm where the unmolded side of lsi is exposed to light , excess current flows. use under sealed condition. 6 specified under following conditions: internal oscillator is used; rf = 180k w 32-levels gray scale mode; gray = 0 co,cl1,flm,m stop; cle = 1 vcc = 3.0v checker board is displayed no access fro cpu 44 t.b.d 7 measured during stand-by mode. vcc = 3.0v 8 specified under following conditions: internal power supply circuit is used. resister value is 5m w which is connected between irefm and gnd vcc = 3.0v, vlcd = 15v, irefp = vcc, gref = gnd 9. all electrical characteristic are guaranteed at +85? for die products.
preliminary rev. 1.1e '99.02.10 HD66421 input terminal input enable i/o terminal pins: db7 to db0, flm, m, cl1 output enable data output terminal pins: co figure 47 terminal configuration pins: cs, rs, wr, rd, res, m/s 45 m/s co data
preliminary rev. 1.1e '99.02.10 HD66421 ac characteristics (vcc = 2.2 to 5.5v, gnd = 0v, ta = -40 to +85? note 1 ) clock characteristics item symbol min typ max unit notes oscillation frequency f osc 160 220 280 khz rf = 180k w , vcc = 3.0v external clock frequency f cp 50 400 khz external clock duty cycle duty 45 50 55 % external clock fall time tr 0.2 s external clock rise time tf 0.2 s mpu interface item symbol min typ max unit notes rd low-level width t wrdl 250 ns rd high-level width t wrdh 450 ns wr low-level width t wwrl 190 ns wr high-level width t wwrh 450 ns address setup time t as 20 ns address hold time t ah 20 ns data delay time t ddr 180 ns data output hold time t dhr 20 ns data setup time t dsw 150 ns data hold time t dhw 10 ns reset timing item symbol min typ max unit notes res low-level width t res 1 ms 46 190 ns 250 ns 150 ns 100 ns vcc = 2.2v to 3.0v, 2 vcc = 3.0v to 5.5v, 2 vcc = 2.2v to 3.0v, 2 vcc = 3.0v to 5.5v, 2 vcc = 2.2v to 3.0v vcc = 3.0v to 5.5v vcc = 2.2v to 3.0v vcc = 3.0v to 5.5v figure 44 mpu interface notes. the following load circuit is connected for specification. voh and vol of the timing specification is 1/2 vcc level. output terminal 30pf(includes board capacitance) t wrdl t wrdh t wwrl t wwrh t as t ah t ddr t dhr t dsw t dhw t as t ah rd wr rs,cs db7- db0 4tosc - 450 4tosc - 450 4tosc - 450 4tosc - 450 note 1 all electrical characteristic are guaranteed at +85? for die products. note 2 tosc = 1 / fosc

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